One way of distributing a global clock on a chip is using a hierarchical approach, in which a tuned and balanced tree drives a grid that provides a local clock signal to the components of the chip. Ensuring that this tree-driven grid global clock network is low-skew and low-jitter in the presence of process, voltage, and temperature (PVT) variation is a significant challenge. As clock frequencies increase with the scaling of technology, the problem becomes even more difficult.
One approach is to use standing-wave clock distributions. These have been used at both the board level and the chip level. These designs can reduce clock skew and jitter, and can save power due to the resonance between the clock capacitance and the clock wire inductance. However, standing-wave clock distributions must contend with non-uniform clock amplitude, which may result in skew or make local clock buffering more complex. Traveling-wave clock distributions use coupled transmission line rings to reduce clock skew and jitter, and also benefit from the power advantage of resonance. However, traveling-wave clock distributions have non-uniform phase across the distribution. This makes integration with existing local clocking methodologies difficult.
Another approach is to distribute clock generation by using oscillator array clocks. Distributed clock generation reduces the distance between a clock source and a clock load. However, this approach requires the need for synchronization. This can be done using phase detectors, or by directly coupling the oscillators together using interconnects. Oscillator array clocks are complicated by non-uniform phase, non-uniform amplitude, and/or complex synchronization schemes.